amen zwa, esq.<p>The CPUs' heyday of Moore's Law and Dennard Scaling are over. GPUs and TPUs had saturated the market. Ubiquitous quantum computing is but a pipe dream. So, what's next?</p><p><a href="https://mathstodon.xyz/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FPGA</span></a> and <a href="https://mathstodon.xyz/tags/ASIC" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>ASIC</span></a>, of course, especially considering the steep, upward tick in growth and availability of lower-cost hardware components and higher-capability software tools.</p><p>For over 40 years, these technologies had been in heavy use in the specialised fields of DSP, avionics, I/O, networks, and the like, mainly due to the considerable demands they place upon development costs and engineering skills. But the recent advances in HLS and HDL software, along with low-cost hardware boards, IP blocks, and SoCs, had rendered these technologies competitive with the conventional CPU- and MCU-based approaches, for use in broader, industrial applications.</p><p>It is high time the FPGA/ASIC hardware design courses trickle from the <a href="https://mathstodon.xyz/tags/EE" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>EE</span></a> curriculum down to the <a href="https://mathstodon.xyz/tags/CS" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>CS</span></a> curriculum.</p><p>But then, there are so-called "higher education" institutions that have already replaced instructors with LLMs, so what do I know, really....</p>